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MIPS architecture - Other models and future plans | | MIPS architecture - Other models and future plans: Encyclopedia II - MIPS architecture - Other models and future plans | | Other members of the MIPS family include the R6000, an ECL implementation of the MIPS architecture which was produced by Bipolar Integrated Technology. The R6000 microprocessor introduced the MIPS II instruction set. Its TLB and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market. The RM7000 was a version of the R5000 with a built-i ...
See also:MIPS architecture, MIPS architecture - History, MIPS architecture - MIPS CPU family, MIPS architecture - Applications, MIPS architecture - Other models and future plans, MIPS architecture - MIPS cores, MIPS architecture - MIPS Programming and Emulation, MIPS architecture - Summary of R3000 instruction set, MIPS architecture - Memory to register transfer instructions, MIPS architecture - Register to memory transfer instructions, MIPS architecture - Register to register move instructions, MIPS architecture - Common arithmetic instructions, MIPS architecture - Common logic instructions bitwise, MIPS architecture - Common shift instructions, MIPS architecture - Branching and jump instructions, MIPS architecture - Some other important instructions | | | MIPS architecture, MIPS architecture - Applications, MIPS architecture - Branching and jump instructions, MIPS architecture - Common arithmetic instructions, MIPS architecture - Common logic instructions bitwise, MIPS architecture - Common shift instructions, MIPS architecture - History, MIPS architecture - MIPS CPU family, MIPS architecture - MIPS Programming and Emulation, MIPS architecture - MIPS cores, MIPS architecture - Memory to register transfer instructions, MIPS architecture - Other models and future plans, MIPS architecture - Register to memory transfer instructions, MIPS architecture - Register to register move instructions, MIPS architecture - Some other important instructions, MIPS architecture - Summary of R3000 instruction set | | |
| | | MIPS architecture: Encyclopedia II - MIPS architecture - Other models and future plans
MIPS architecture - Other models and future plans
Other members of the MIPS family include the R6000, an ECL implementation of the MIPS architecture which was produced by Bipolar Integrated Technology. The R6000 microprocessor introduced the MIPS II instruction set. Its TLB and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market. The RM7000 was a version of the R5000 with a built-in 256kB level 2 cache and a controller for optional level three cache. It was primarily targeted at embedded designs, including SGI's graphics processors and various networking solutions, primarily by Cisco. The R9000 name was never used.
At one time SGI had intended to move off the MIPS platform to the Intel Itanium, and development was to have ended with the R10000. The ever-longer delays in introducing the Itanium meant that the installed base of MIPS-based machines continued to increase. By 1999 it was clear that development had ended too soon, and the R14000 and R16000 were created as a result. SGI has hinted at a more complex R8000 style FPU for later R-series, and a dual core processor is probable. Low power consumption / heat dissipation will continue to be a focus.
Other related archives1981, 1985, 1988, 1994, 1995, ADSL, AMD, AMD 29000, ARM architecture, Acer, August 2000, BSD, Bipolar Integrated Technology, Broadcom, By the late 1990s, CISC, Cisco, Control Data, DDR, DEC, DEC Alpha, DECstation, DeskStation, Digital Equipment Corporation, ECL, FPU, Freescale, GXemul, HyperThreading, IA64, IDT, IRIX, Instructions, Intel, Irix, Itanium, John L. Hennessy, Lexra, Linux, MIPS Computer Systems Inc., MIPS Computer Systems, Inc., MIPS Technologies, MMU, Microsoft, Motorola, Motorola 68000, NEC, Nintendo 64, Olivetti, PMC-Sierra, Philips, PlayStation, PlayStation 2, PlayStation Portable, PowerPC, Quantum Effect Devices, R2000, RISC, RISC/os, SCSI, SGI, SGI Indy, SGI O2, SIMD, SINIX, SOC, SPARC, SPIM, SRAM, Siemens-Nixdorf, Sony, Stanford University, StrongARM, Sun Microsystems, System V, TLB, Thumb, Toshiba, UNIX, Ultrix, VUPs, Windows CE, Windows NT, big-endian, cable modems, cache, cache coherency, computer architecture, deep pipelining, double precision, embedded, embedded processor, embedded systems, framebuffers, front side bus, gate count, hand-held computers, instruction pipelines, instruction set, laser printer, little-endian, multithreading, operating systems, out-of-order execution, robots, routers, set-top boxes, single precision, smartcards, start-up, superscalar, systems-on-a-chip, workstation, workstations
 Adapted from the Wikipedia article "Other models and future plans", under the G.N U Free Docmentation License. Please also see http://en.wikipedia.org/wiki |
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