IBM 1620: Encyclopedia II - IBM 1620 - Hardware implementation

IBM 1620 - Hardware implementation

Most of the logic circuitry of the 1620 was a type of resistor-transistor logic (RTL) using "drift" transistors (a type of transistor invented by Herbert Kroemer in 1957) for their speed, that IBM referred to as SDTRL. Other IBM circuit types used were referred to as: Alloy (some logic, but mostly various non-logic functions, named for the kind of transistors used), CTRL (another type of RTL, but slower than SDTRL), CTDL (a type of diode-transistor logic (DTL)), and DL (another type of RTL, named for the kind of transistor used, "drift" transistors). Typical logic levels of all these circuits (S Level) were: high – 0V to -0.5V, low – -6V to -12V. Transmission line logic levels of SDTRL circuits (C Level) were: high – 1V, low – -1V. Relay circuits used either of two logic levels (T Level) were: high – 51V to 46V, low – 16V to 0V or (W Level) were: high – 24V, low – 0V.

These circuits were constructed of individual discrete components mounted on single sided paper-epoxy printed circuit boards 2.5 by 4.5 inches (38 by 114 mm) with a 16 pin gold plated edge connector, that IBM referred to as SMS cards (Standard Modular System). The amount of logic on one card was similar to that in one 7400 series SSI or simpler MSI package (e.g., 3 to 5 logic gates or a couple of flip-flops).

These boards were inserted in sockets on racks, that IBM referred to as gates. The machine had the following "gates" in its basic configuration:

• "Gate A" - Forward hinged gate that swings out the back for access, after "Gate B".
• "Gate B" - Rear hinged gate that swings out the back for access.
• "Gate C" - Slides out back for access. Console Typewriter interface. Mostly relay logic.
• "Gate D" - Slides out back for access. Standard I/O interface.

There were two different types of core memory used in the 1620:

• Main memory
  • Coincident Current X-Y Line addressing
    • 20,000, 40,000, or 60,000 Digits
  • 12 bit, even-odd Digit Pair
  • 12 one bit planes in each module, 1 to 3 modules
    • 10,000 cores per plane
• Memory Address Register Storage (MARS) memory
  • Word Line addressing
    • 16 Words, minimum of 8 used in basic configuration
    • Single Word read, multiple Word clear/write
  • 24 bit, 5 Digit decimal Memory Address (no 8 - Ten Thousand bit stored)
  • 1 plane
    • 384 cores

The address decoding logic of the Main memory also used two planes of 100 pulse transformer cores per module to generate the X-Y Line half-current pulses.

There were two models of the 1620, each having totally different hardware implementations:

• IBM 1620 I
• IBM 1620 II

Adapted from the Wikipedia article "Hardware implementation", under the G.N U Free Docmentation License. Please also see http://en.wikipedia.org/wiki