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Logical effort - Delay in an inverter | | Logical effort - Delay in an inverter: Encyclopedia II - Logical effort - Delay in an inverter | | CMOS Inverter
The logical effort of an inverter is defined to be g = 1 by noting that the input capacitance of a minimum size inverter has an NMOS input capacitance of 1, while the PMOS input capacitance is two. Thus g = 3/3, and g = 1. Remember: electron mobility is greater than hole mobility.
The parasitic of an inverter is p = 1. If γ = 2, and the inverter drives an equivalent inverter, then:
d = ...
See also:Logical effort, Logical effort - Derivation of delay in a logic gate, Logical effort - Delay in an inverter, Logical effort - Delay in a NAND gate, Logical effort - Intrinsic properties of a circuit | | | Logical effort, Logical effort - Delay in a NAND gate, Logical effort - Delay in an inverter, Logical effort - Derivation of delay in a logic gate, Logical effort - Intrinsic properties of a circuit, Sutherland, Ivan E, et. al. Logical Effort: Designing Fast CMOS Circuits. 1999. | | |
| | | Logical effort: Encyclopedia II - Logical effort - Delay in an inverter
Logical effort - Delay in an inverter
CMOS Inverter
The logical effort of an inverter is defined to be g = 1 by noting that the input capacitance of a minimum size inverter has an NMOS input capacitance of 1, while the PMOS input capacitance is two. Thus g = 3/3, and g = 1. Remember: electron mobility is greater than hole mobility.
The parasitic of an inverter is p = 1. If γ = 2, and the inverter drives an equivalent inverter, then:
d = gh + p = (1)(1) + 1 = 2
 Adapted from the Wikipedia article "Delay in an inverter", under the G.N U Free Docmentation License. Please also see http://en.wikipedia.org/wiki |
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