Dynamic random access memory: Encyclopedia - Dynamic random access memory

Dynamic random access memory

DRAM is a type of random access memory that stores each bit of data in a separate capacitor. The number of electrons stored in the capacitor determines whether the bit is considered 1 or 0. As the capacitor leaks electrons, the information gets lost eventually, unless the charge is refreshed periodically. Because it must be refreshed periodically, it is a dynamic memory as opposed to SRAM and other static memory. Also, since DRAM loses its data when the power supply is removed, it is in the class of volatile memory devices. DRAM is also in the class of solid-state memory.

Dynamic random access memory - History of DRAM

The first DRAM cell was invented in 1966 by Robert Dennard, a researcher at IBM's Thomas J. Watson Research Center. This cell worked like most modern DRAM cells in that data must be refreshed to restore the capacitance and the data was destroyed after a read operation and must be rewritten. Despite DRAM cells being ubiquitous today, Dennard was one of few people at the time who believed an effective DRAM cell could be developed.

Dynamic random access memory - Principle of operation of DRAM

DRAM is usually arranged in a square array of capacitors, as shown in the illustrations here which show a simple example with only 4 by 4 cells (more typical DRAM has 1024 by 1024 cells). During a read of any cell, the entire row is read out and written back in (refresh). During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.

DRAM cells are smaller and therefore cheaper than SRAM cells, which operate by flip-flops rather than capacitors (1 transistor and 1 capacitor take less space than 6 transistors).

Typically, manufacturers specify that each row should be refreshed every 64 ms or less. Refresh logic is commonly used with DRAMs to automate the periodic refresh. This makes the circuit more complicated, but this drawback is usually outweighed by the fact that DRAM is much cheaper than SRAM. Some systems refresh every row in a tight loop that occurs once every 64 ms. Other systems refresh one row at a time -- for example, a system with 2^13 = 8192 rows would have a refresh rate of one row every 7.8 µs (64 ms / 8192 rows). Both methods require some sort of counter to keep track of which row is the next to be refreshed. Some DRAM chips include that counter; other kinds require external refresh logic to hold that counter. (Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes [1].)

Another alternative to DRAM is Flash memory. Currently available flash memory is slightly cheaper per bit than DRAM, is non-volatile, but is much slower than DRAM when reading (and exceedingly slower than DRAM when writing), and will eventually wear out after several thousand write cycles.

Dynamic random access memory - Errors and Error Correcting

It is possible that electrical or magnetic interference inside a computer system could cause a single bit of DRAM to spontaneously flip to the opposite state. Some research has shown that the majority of one-off ("soft") errors in DRAM chips occur as a result of cosmic rays, which may change the contents of one or more memory cells, or interfere with the circuitry used to read/write them - there is some concern that as DRAM density increases further, and thus the components on DRAM chips get smaller, whilst at the same time operating voltages continue to fall, DRAM chips will be affected by such radiation more frequently - since lower energy particles will be able to change a memory cell's state. On the other hand, smaller cells make smaller targets, and moves to technologies such as SOI may make individual cells less susceptible and so counteract, or even reverse this trend.

This problem can be mitigated by using DRAM modules that include extra memory bits - ECC-capable memory controllers can then use error detection functions to detect when it happens, and possibly ECC functions to narrow down exactly which bit was in error and correct it. Error-correction functions in PCs can typically detect, and correct errors of a single bit per 64 bit word, and detect (but not correct) errors of two or more bits per 64 bit word. Some systems also 'scrub' the errors, by writing the corrected version back to memory. The BIOS in some computers, and operating systems such as Linux, allow counting of detected and corrected memory errors, in part to help identify failing memory modules before the problem becomes catastrophic.

Dynamic random access memory - Special Types of DRAM

Dynamic random access memory - Fast Page Mode DRAM FPM

Fast page mode DRAM is also called FPM DRAM, Page mode DRAM, Fast page mode memory, or Page mode memory.

In page mode, a row of the DRAM can be kept "open", so that successive reads or writes within the row do not suffer the delay of precharge and accessing the row. This increases the performance of the system when reading or writing bursts of data.

Static column is a variant of page mode in which the column address does not need to be strobed in.

Nibble mode is another variant in which four sequential locations within the row can be accessed.

Dynamic random access memory - Video DRAM VRAM

VRAM is a dual-ported version of DRAM formerly used in graphics adaptors. It is now almost obsolete, having been superseded by SDRAM and SGRAM. VRAM has two paths (or ports) to its memory array that can be used simultaneously.

The first port, the DRAM port, is accessed as with plain DRAM. The second port, the video port, is read-only, and is dedicated to feeding a fast stream of data to the display. To use the video port, the controller first uses the DRAM port to select the row of the memory array that is to be displayed. The VRAM then copies that entire row to an internal shift-register. The controller can then continue to use the DRAM port for drawing objects on the display. Meanwhile, the controller feeds a clock called the shift clock (SCLK) to the VRAM's video port. Each SCLK pulse causes the VRAM to deliver the next item of data, in strict address order, from the shift-register to the video port. For simplicity, the graphics adapter is usually designed so that the contents of a row, and therefore the contents of the shift-register, corresponds to a complete horizontal line on the display.

Dynamic random access memory - Window RAM WRAM

Window RAM or WRAM is an obsolete type of semiconductor computer memory that was designed to replace video RAM (VRAM) in graphics adapters. It was developed by Samsung and also marketed by Micron Technology, but had only a short market life before being superseded by SDRAM and SGRAM.

WRAM has a dual-ported dynamic RAM structure similar to that of VRAM, with one parallel port and one serial port, but has extra features to enable fast block copies and block fills (so-called window operations). It was often clocked at 50 MHz. It has a 32-bit wide host port to enable optimal data transfer in PCI and VESA Local Bus systems. Typically WRAM was 50% faster than VRAM, but with costs 20% lower. It is sometimes erroneously called Windows RAM, because of confusion with the Microsoft Windows operating systems, to which it is unrelated.

It was used by Matrox on both their MGA Millenium and Millenium II graphics cards.

Dynamic random access memory - Extended Data Out EDO DRAM

EDO DRAM is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved speed. It was 5% faster than Fast Page Mode DRAM, which it began to replace in 1993.

Single-cycle EDO has the ability to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM access within the same page takes two clock cycles instead of three, once the page has been selected. EDO's speed and capabilities allowed it to somewhat replace the then-slow L2 caches of PCs. It created an opportunity to reduce the immense performance loss associated with a lack of L2 cache, while making systems cheaper to build. This was also good for notebooks due to difficulties with their limited form factor, and battery life limitations. Performance was still lost though, and an EDO system with L2 cache was tangibly faster than the older FPM/L2 combination.

Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM.

EDO was sometimes referred to as Hyper Page Mode.

Dynamic random access memory - Burst EDO BEDO DRAM

An evolution of the former, Burst EDO DRAM, could process four memory addresses in one burst, for a maximum of 5-1-1-1, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipelined stage allowing page-access cycle to be divided into two components. During a memory-read operation, the first component accessed the data from the memory array to the output stage (second latch). The second component drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, faster access time is achieved (up to 50% for large blocks of data) than with traditional EDO.

Although BEDO DRAM showed additional optimization over EDO, by the time it was available, the market had made a significant investment towards synchronous DRAM, or SDRAM [2].

Dynamic random access memory - Multibank DRAM MDRAM

Multibank RAM applies the interleaving technique for main memory to second level cache memory to provide a cheaper and faster alternative to SRAM. The chip splits its memory capacity into small blocks of 256 kB and allows operations to two different banks in a single clock cycle.

This memory was primarily used in graphic cards with Tseng Labs ET6x00 chipsets, and was made by MoSys. Boards based upon this chipset often used the unusual RAM size configuration of 2.25 MB, owing to MDRAM's ability to be implemented in various sizes more easily. This size of 2.25 MB allowed 24-bit color at a resolution of 1024x768, a very popular display setting in the card's time.

Dynamic random access memory - Synchronous Graphics RAM SGRAM

SGRAM is a specialized form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies.

SGRAM and SDRAM became the most popular types of DRAM at the end of the 1990s, and well into the first decade of the 2000s.

Dynamic random access memory - Synchronous Dynamic RAM SDRAM

SDRAM (SDR SDRAM)is an improved type of DRAM. Whilst DRAM has an asynchronous interface, meaning that it reacts immediately to changes in its control inputs, SDRAM has a synchronous interface, meaning that it waits for a clock pulse before responding to its control inputs. The clock is used to drive an internal finite state machine that can pipeline incoming commands. This allows the chip to have a more complex pattern of operation than plain DRAM.

Pipelining means that the chip can accept a new command before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears a fixed number of clock pulses after the read command. It is not necessary to wait for the data to appear before sending the next command. This delay is called the latency, and is an important parameter to be considered when purchasing SDRAM for your computer.

SDRAM for PCs is rated for its potential maximum clock rate. Speeds included PC-66, PC-100, and PC-133, representing 66 MHz, 100 MHz, and 133 MHz. There were additional unofficial speeds for enthusiast SDRAM parts, such as PC150, for 150 MHz.

SDRAM was introduced in 1997, and by the 2000s had replaced plain DRAM in modern computers, because of its greater speed.

Dynamic random access memory - Direct Rambus DRAM DRDRAM

Direct Rambus DRAM (DRDRAM), often called RDRAM, is internally similar to DDR SDRAM, but uses a special method of signaling developed by the Rambus Company that allows faster clock speeds. The high clock speed does not directly translate into high bandwidth because Rambus combines this high clock with a very narrow bus. This makes the high clock rate more stable, and easier and cheaper to implement. However, RDRAM comes with a relatively high access latency which often negates the technology's potential performance advantages. RDRAM chips are packaged on modules called RIMMs, which are not compatible with the DIMMs used for plain SDRAM. Intel licensed the Rambus technology and introduced chipsets with RDRAM support.

While RDRAM technology was designed to be cheaper to implement on the system level, the RIMM sticks were not easy to manufacture in the beginning. Similar to how the Pentium Pro CPU could not be tested until both cores were installed, the RIMM sticks needed to be completely assembled before testing could be performed. This created the scenario where if just one of the RDRAM chips was faulty, the entire stick had to be thrown away.

Early Intel Pentium 4 systems could only use RDRAM or slow SDR SDRAM, but as RDRAM prices remained very high, Intel finally introduced support for DDR. (VIA Technologies had a DDR chipset for the Pentium 4 before this, but legal threats regarding licensing put motherboard manufacturers off using it. VIA then decided to make their own boards with the chipset but these didn't gain much traction either) RDRAM all but disappeared in new systems around 2003, due to the availability of DDR chipsets for the Pentium 4 and the far lower cost of DDR SDRAM.

Nintendo used RDRAM in its Nintendo 64 system, where it was praised for its incredible bandwidth at low cost while chastised for its horrible latencies (Gamecube's use of ultra-low latency 1T-SRAM may be a direct result of developer feedback on RDRAM). Cirrus Logic utilized RDRAM for their first 3D accelerator chip, the Laguna3D, however the chip's performance was sub par. Sony used RDRAM in its PlayStation 2 video game console, and announced it would use Rambus's XDR memory in its PlayStation 3, expected in 2006.

Dynamic random access memory - Double Data Rate DDR SDRAM

Double data rate (DDR) SDRAM was a later development of SDRAM, used in PC memory from 2000 onwards. All types of SDRAM used a clock signal that was a square wave. This meant that the clock alternated regularly between one voltage (low) and another (high), usually millions of times per second. Plain SDRAM, like most synchronous logic circuits, acted on the low-to-high transition of the clock and ignored the opposite transition. DDR SDRAM acted on both transitions, thereby halving the required clock rate for a given data transfer rate.

The DDR SDRAM standard is evolving, from DDR to DDR2 to DDR-3. At the time of writing (January 2006), DDR is still the main memory standard, but DDR2 is supported by some chipsets and is seeing increased use. DDR2 is expected to become the major standard in 2006, while DDR-3 is under development and standardization within JEDEC has started. The difference between DDR, DDR2, DDR-3 is mostly in differing supply voltages, different speed classes, as well as some changes in the exact specification of the interface.

• DDR: supply voltage VDD = 2.5 V
• DDR2: supply voltage VDD = 1.8 V
• DDR-3: supply voltage VDD not yet standardized (draft specifications call for 1.2 to 1.6 V)

DDR SDRAM for PC is typically rated by performance, though it is sometimes also rated by its DDR clock rate. Speeds have ranged from PC1600, PC2100, PC2700, and PC3200, with the number representing the theorectical maximum data throughput in megabytes per second. DDR is also sometimes seen with the ratings DDR200, DDR266, DDR333, and DDR400, representing the doubled clock rate. Like SDR SDRAM, there have been unofficial speed ratings, such as PC3500 and PC4000, used by enthusiasts to run their systems out-of-spec for greater performance.

DDR2 is rated similarly to DDR, such as PC2-3200 and PC2-4200, again directly relating to theoretical memory throughput.

Dynamic random access memory - Quad Data Rate QDR SDRAM

Quad Data Rate (QDR) SDRAM

Dynamic random access memory - Pseudostatic RAM PSRAM

PSRAM is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM.

Some DRAM components have a "self-refresh mode". While this involves much of the same logic that is needed for pseudo-static operation, this mode is often equivalent to a standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, not to allow operation without a DRAM controller as is the case with PSRAM.

Dynamic random access memory - See Also

• DRAM price fixing

Adapted from the Wikipedia article "Dynamic random access memory", under the G.N U Free Docmentation License. Please also see http://en.wikipedia.org/wiki